1. Field of the Invention
This invention relates to computer systems and more particularly to memory addressing mechanisms and techniques employed within computer systems.
2. Description of the Relevant Art
Computer systems based on the particularly popular model 80486 microprocessor allow memory accesses on a per-byte basis. Within 80486 based systems, one byte of data comprises 8-bits. Since the data bus of the model 80486 has a width of 32-bits, it is possible to transfer a total of four bytes of data at a time. A given combination of four bytes of data transferrable simultaneously on the data bus are referred to as a "doubleword". A set of address signals from the microprocessor are used to select the doubleword being referenced during a particular bus cycle, and four byte enable signals are provided to indicate the particular bytes of the addressed doubleword that are valid during the cycle.
FIG. 1 illustrates a block diagram of a portion of a typical model 80486-based computer system 100. The computer system 100 of FIG. 1 includes a memory controller 102 coupled to a microprocessor (CPU) 104 and a system memory 106. Microprocessor 104 includes an execution core 110 that implements a predetermined instruction set and a bus control unit 112 that controls the generation of a local bus address signal labeled LA[31:2] and a byte enable signal BE[3:0].
System memory 106 is illustrative of a static RAM or a dynamic RAM memory subsystem. Memory control unit 102 orchestrates the transfer of data, address, and control signals between microprocessor 104 and system memory 106.
Internally, execution core 110 of microprocessor 104 generates an addressing signal A[31:0] which specifies memory locations on a per-byte basis during memory access cycles. Since execution core 110 is capable of generating single-byte memory bus cycles, two byte memory bus cycles, or four-byte memory bus cycles, the execution core 110 also generates a memory size signal labeled MEMSIZE [1:0] which indicates the number of bytes to be accessed during execution of a given cycle. In response to an internal memory access cycle, bus control unit 112 controls the generation of the local bus address signal LA[31:2] to specify the particular doubleword(s) being accessed. The bus control unit 112 further decodes the two lower-order addressing signals A[1:0] and the MEMSIZE[1:0] signal to generate an appropriate byte enable signal BE[3:0]. The byte enable signal BE[3:0] specifies the bytes within the particular addressed doubleword that are enabled during a particular memory cycle. The memory control unit 102 correspondingly monitors the local bus address signal LA[31:2] and the byte enable signal BE[3:0] during operation to generate appropriate address control signals on the memory bus to access system memory 106.
For the computer system of FIG. 1, the generation of an internal memory reference by execution core 110 that results in a "misaligned memory access" requires two external memory cycles by control unit 112. A misaligned memory access exists when a memory cycle is generated by execution core 110 that requires the transfer of selected bytes of different consecutive doublewords, as defined by the memory mapping of the particular system. Two external memory cycles are required to execute an instruction involving a misaligned memory address since the address signal LA[31:2] as generated by bus control unit 112 is only capable of specifying a single doubleword at a time, with the byte enable signals specifying the particular bytes of the addressed doubleword. For example, consider a situation in which an instruction is encountered by execution core 110 to write four bytes of data starting at the byte address location 003:H (i.e., A[31:0] =003:H). FIG. 2A illustrates the external local bus cycles generated by bus control unit 112 during the execution of such a cycle. FIG. 2B is an exemplary memory map that illustrates the apparent segregation of doublewords (along with the constituent bytes of each) within system memory 106. It is noted that each doubleword is segregated in accordance with the local bus address signal LA[31:2]. That is, the local bus address signal LA[31:2] specifies a particular doubleword location of system memory 106. Each row of the memory map of FIG. 2B represents a separate doubleword location, and each row is divided into four sections which are representative of the separate bytes of each doubleword. It is noted that each byte location is indirectly specified by the internal address signal A[31:0], but cannot be individually specified by the local bus address signal LA[31:2] (i.e., byte 3 of doubleword LA[31:2] =000:H corresponds to byte address location A[31:0] =003H).
As illustrated within FIGS. 2A and 2B, to effectuate a requested operation involving a write of four bytes of data (labelled bytes "A", "B", "C" and "D") starting at address location A[31:0] =003:H, bus control unit 112 drives the local bus address signal LA[31:2] with a value of 001:H during a first bus cycle 202. Bus control unit 112 simultaneously drives the byte enable signals BE[3:0] with a value of 1000:B, and asserts appropriate control signals to effectuate a memory write cycle. The bus control unit 112 further causes the three bytes of data (byte "B", byte "C", and byte "D") to be appropriately driven on data lines D[23:0]. The data is thereby written into the three lower-order byte locations of the addressed doubleword (i.e., LA[31:2] =001:H). During a subsequent bus cycle 204, bus control unit 112 drives the local bus address lines A[31:2] with a value of 000:H, and simultaneously drives the byte enable signals BE[3:0] with a value of 0111:B. Upon this cycle, byte "A" is driven on data lines [24:31] by bus control unit 112 and is written into the highest-order byte location of the doubleword LA[31:2] =000:H. Thus, as illustrated within FIG. 2B, the three lower-order bytes of the doubleword address location 001:H are written with valid data during the first memory cycle, and the highest-order byte of doubleword address location 000:H is written with valid data during the second memory cycle. As a result, the four bytes of data "A", "B", "C", and "D" are ultimately written to system memory 106 starting at the byte address location A[31:0] =003H.
Unfortunately, the requirement of executing two memory cycles when a memory access on a misaligned byte boundary occurs increases the time required to complete the instruction and reduces the bandwidth of the local bus. As a result, overall performance of the computer system may be degraded.